Semiconductor device and manufacturing method thereof

ABSTRACT

A sidewall-insulation film  9  is provided on a side surface of a first opening portion  8   a  formed in a base extraction electrode  5 B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film  9  extends so as to protrude from a surface opposite to a semiconductor substrate  1  toward a main surface of the semiconductor substrate  1  in the base extraction electrode  5 B, and protruded length thereof is set to be equal to or smaller than one half of thickness of the insulation film  4  interposed between the main surface of the semiconductor substrate  1  and a lower surface of the base extraction electrode  5 B.

TECHNICAL FILED OF THE INVENTION

The present invention relates to a semiconductor device and amanufacturing technique therefor and particularly to a techniqueeffectively applied to a semiconductor device having a hetero-junctionbipolar transistor (hereinafter abbreviated as “HBT”) and to amanufacturing method for the semiconductor device.

BACKGROUND OF THE INVENTION

A HBT technique has been examined primarily for improving the high-speedperformance of the bipolar transistor. A HBT forming method examined bythe present inventors is, for example, described as follows.

First, on a semiconductor substrate, a silicon nitride film, apolycrystalline silicon film for forming a base electrode, and a siliconoxide film are deposited in order of this subsequently to a lower layer.Then, after forming a first opening-forming photoresist pattern on thesilicon oxide film, the silicon oxide film and the polycrystallinesilicon film that are exposed therefrom are etched in order of this.Thereby, a first opening portion is formed in the silicon nitride filmand the polycrystalline silicon film in such a manner as to expose aportion of an upper surface of the silicon nitride film from a bottomportion. Then, after forming a sidewall-insulation film on a sidesurface of the first opening portion, a second opening portion greaterin a plane size than the first opening portion is formed in such amanner as to communicate with the first opening portion by removing thesilicon nitride film through the first opening portion. From this secondopening portion, a main surface of the semiconductor substrate and aportion of a bottom surface side of the polycrystalline silicon film areexposed. Then, in the second opening portion, a dissimilar crystallinelayer such as silicon-germanium (SiGe) is made to grow selectively by anepitaxial method. This dissimilar crystalline layer is formed by beingmade to grow from both an exposed surface side of the semiconductorsubstrate and an exposed surface side of the polycrystalline siliconfilm. Thereafter, a polycrystalline silicon film for an emitterelectrode is embedded in the first opening portion, and impurities inthe polycrystalline silicon film are diffused in the dissimilarcrystalline layer to form an emitter region. Note that these HBT formingtechniques are disclosed in, for example, Japanese Patent PublicationNo. 2705344 or Fumihiko Sato, et al., “A Super Aligned Selectively GrownSiGe Base (SSSB) Bipolar Transistor Fabricated by Cold-Wall UHV/CVDTechnology”, IEEE Trans. ED, Vol. 41, pp. 1373-1378 (1994).

However, it has been found at first by the investigations of the presentinventors that the above HBT forming method has the following problems.That is, in the above method, an upper portion of the silicon nitridefilm on the bottom surface of the first opening portion is slightlyetched when the first opening portion is formed. In particular, if thephotoresist film is used as an etching mask at the time of forming thefirst opening portion, the silicon nitride film is easily etched becauseit is impossible to provide a sufficiently high selective ratio of thepolycrystalline silicon film to the silicon nitride film. If the secondopening portion is formed after forming the sidewall-insulation film onthe side surface of the first opening portion under this condition asdescribed above, a lower portion of the sidewall-insulation film becomesgreatly protruded to a side of the second opening portion along adirection orthogonal to the main surface of the semiconductor substrate.If the above-mentioned dissimilar crystalline layer is made to growunder this condition, the growth of the dissimilar crystalline isblocked by the protrusion of the sidewall-insulation film. Inparticular, since the growth of the dissimilar crystalline is blocked ata portion of a bottom surface side of the polycrystalline silicon filmfor forming the base electrode, the dissimilar crystalline layer isunsuccessfully connected to the polycrystalline silicon film, wherebythere is the problem that base resistance is greatly increased.

An object of the present invention is to provide a technique for beingcapable of improving reliability of a semiconductor device having a HBT.

The above and other objects and novel features of the present inventionwill become apparent from the description of this specification and thedrawings.

DISCLOSURE OF THE INVENTION

Outlines of representative ones of inventions disclosed by the presentapplication will be briefly described as follows.

That is, the present invention intends to prevent thesidewall-insulation film formed on the side surface of the first openingportion from blocking the growth of the dissimilar crystalline layerformed in the second opening portion communicating with the firstopening portion.

Also, outlines of other representative ones of inventions disclosed bythe present application will be briefly described as follows.

That is, the present invention has the length of a portion protrudingfrom the inside of the second opening portion longer than zero and equalto or smaller than one half the height of the second opening portion, inthe sidewall-insulation film formed on the side surface of the firstopening portion.

Also, the present invention has the first opening portion formed byusing a hard mask as an etching mask without using a photoresist film asan etching mask.

In addition, the present invention has the sidewall-insulation filmprovided on each side surface of the first opening portions, which areopened in the polycrystalline film for forming the base electrode andthe insulation film laminated thereon, in such a manner as to overlapwith the insulation film exposed from each side face of the firstopening portions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing a principal portion in amanufacturing process of a semiconductor device according to anembodiment of the present invention.

FIG. 2 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.1.

FIG. 3 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.2.

FIG. 4 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.3.

FIG. 5 is an enlarged sectional view showing a principal portion in themanufacturing process of the semiconductor device of FIG. 4.

FIG. 6 is an enlarged sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.5.

FIG. 7 is an enlarged sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.6.

FIG. 8 is an enlarged sectional view showing a principal portion in themanufacturing process of the semiconductor device following FIG. 9.

FIG. 9 is an enlarged sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.8.

FIG. 10 is an enlarged sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.9.

FIG. 11 is an enlarged sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.10.

FIG. 12 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.11.

FIG. 13 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.12.

FIG. 14 is an enlarged sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.13.

FIG. 15 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.14.

FIG. 16 is a plan view showing a principal portion in the manufacturingprocess of the semiconductor device of FIG. 15.

FIG. 17 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device, which the presentinventors have examined.

FIG. 18 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.17.

FIG. 19 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.18.

FIG. 20 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.19.

FIG. 21 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.20.

FIG. 22 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.21.

FIG. 23 is a sectional view showing a principal portion in amanufacturing process of a semiconductor device, which is illustrated toexplain problems arising in the manufacturing process of eachsemiconductor device of FIGS. 17 to 22.

FIG. 24 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.23.

FIG. 25 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.24.

FIG. 26 is a sectional view showing a principal portion in themanufacturing process of the semiconductor device subsequently to FIG.25.

FIG. 27 is a graph indicating gammel plots of a transistor withlink-base contact failure and a normal transistor.

FIG. 28 is a sectional view showing a principal portion of asemiconductor substrate to explain a phenomenon in which an etchingselective ratio of a polycrystalline silicon film to a underlyinginsulation film drops if a photoresist film is used as an etching maskin etching the polycrystalline silicon film by using a chlorine-basedgas.

FIG. 29 is an explanatory view for explaining a phenomenon in which anetching selective ratio of a polycrystalline silicon film to aunderlying insulation film drops if a photoresist film is used as anetching mask in etching the polycrystalline silicon film by using achlorine-based gas.

FIG. 30 is an explanatory view for explaining a phenomenon in which anetching selective ratio of a polycrystalline silicon film to aunderlying insulation film drops if a photoresist film is used as anetching mask in etching the polycrystalline silicon film by using achlorine-based gas.

FIG. 31 is an explanatory view for explaining a phenomenon in which anetching selective ratio of a polycrystalline silicon film to aunderlying insulation film drops if a photoresist film is used as anetching mask in etching the polycrystalline silicon film by using achlorine-based gas.

BEST MODE FOR CARRYING OUT THE INVENTION

In an embodiment described below, when referring to the number ofelements (including number of pieces, values, amounts, ranges, or thelike), the number of elements is not limited to a specific number unlessotherwise stated, or except the case where the number is apparentlylimited to a specific number in principle, or the like. The numberlarger or smaller than the specified number is also applicable. Also, inthe embodiment described below, it goes without saying that thecomponents (including element steps or the like) are not alwaysessential unless otherwise stated, or except the case where thecomponents are apparently essential in principle, or the like.Similarly, in the embodiment described below, when the shape of thecomponents and the like, or the positional relation and the likethereof, or the like are mentioned, the substantially approximate andsimilar shapes and the like are included therein unless otherwisestated, or except the case where it can be conceived that they areapparently excluded in principle, or the like. This condition is alsoapplicable to the numerical value and the range described above. Inaddition, components having the same functions are denoted by the samereference symbols throughout the drawings for describing the embodiment,and the repetitive description thereof will be omitted.

First, a description will be made of one example of an HBT(hetero-junction bipolar transistor) forming method which the presentinventors have examined. FIGS. 17 through 22 show sectional views of aprincipal portion in a HBT forming process thereof. As shown in FIG. 17,on or over a p-type semiconductor substrate 50, an n-type collectorembedding region 51 of the HBT, an n⁻-type collector region 52 of theHBT, and an n⁺-type collector extraction region 53 are formed. On a mainsurface of the semiconductor substrate 50, an isolation section 54 isformed. In addition, over the main surface of the semiconductorsubstrate 50, a silicon nitride film 55, a polycrystalline silicon film56 for forming an external base electrode, a polycrystalline siliconfilm 57 for a collector extraction electrode, and a silicon oxide film58 are formed. Note that a silicon oxide film may be used for thesilicon nitride film 55 and a silicon nitride film may be used for thesilicon oxide film 58.

After forming a photoresist pattern 59 on the silicon oxide film 58 sothat an emitter opening region is exposed and a region other than theemitter opening region is covered, the photoresist pattern 59 is used asan etching mask to continuously etch, by an anisotropic dry-etchingmethod, the silicon oxide film 58 and the polycrystalline silicon film56 exposed from the emitter opening region. By doing so, as shown inFIG. 18, a first opening portion 60, from which a portion of an uppersurface of the silicon nitride film 55 is exposed, is formed andthereafter the photoresist pattern 59 is removed. Subsequently, asilicon oxide film is deposited over the main surface of thesemiconductor substrate 50 and is etched back to form a firstsidewall-insulation film 61 a on an inner wall surface of the firstopening portion 60 as shown in FIG. 19. Then, by performing awet-etching treatment to the semiconductor substrate 50 by, for example,phosphoric acid, a portion of the silicon nitride film 55 is removedthrough the first opening portion 60. At this time, a treatment isperformed to such an extent as to etch even the silicon nitride film 55under the polycrystalline silicon film 56. Thereby this, as shown inFIG. 20, a second opening portion 62 larger than the first openingportion 60 is formed. Subsequently, as shown in FIG. 21, a dissimilarcrystalline layer 63 such as silicon-germanium (SiGe) is made toepitaxially grow in the second opening portion 62 with portions of thesemiconductor substrate 50 and polycrystalline silicon film 56 beingexposed in the second opening portion 62. At this time, a crystallineSiGe layer 63 a grows over the semiconductor substrate 50 and apolycrystalline SiGe layer 63 b grows on an exposed surface of thepolycrystalline silicon film 56. Thereafter, a silicon oxide film isdeposited over the main surface of the semiconductor substrate 50 and isetched back, as shown in FIG. 22, to form a second sidewall-insulationfilm 61 b on a side surface of the first sidewall-insulation film 61 aprovided on the inner wall of the first opening portion 60. Then, asemiconductor film 64 made from single crystalline silicon orpolycrystalline silicon is made to epitaxially grow in the first openingportion 60. Then, after forming contact holes 65 in the silicon oxidefilm 58, electrodes 66, 67, and 68 are formed.

However, the present inventors have found out at first that this HBTforming method has the following problems. FIGS. 23 through 26 aresectional views showing a principal portion in the HBT forming processto explain the problems. FIG. 23 is a sectional view showing a principalportion of the semiconductor substrate 50 in the same process as that ofFIG. 18 as described above. FIG. 18 illustrates an ideal state notscraped at an upper portion of the silicon nitride film 55 that is thebottom surface of the first opening portion 60. However, in actuality,as shown in FIG. 23, a portion of the silicon nitride film 55 that isthe bottom surface of the first opening portion 60 is etched at ananisotropic overetching stage. This etching amount varies depending onetching apparatuses. However, if the photoresist film is generally usedas an etching mask, the etching selective ratio of the polycrystallinesilicon film to silicon nitride film is reduced remarkably. The reasonswill be later described. For example, in a high-density plasma-etchingapparatus using a C1-based gas, the selective ratio is 7. FIG. 24 is asectional view showing a principal portion of the semiconductorsubstrate 50 in the same process as that in FIG. 19. In FIG. 24, a lowerportion of the first sidewall-insulation film 61 a on the side surfaceof the first opening portion 60 overlaps with the side surface of thescraped portion of the silicon nitride film 55. Under this state, asshown in FIG. 25, if a portion of the silicon nitride film 55 isretracted by a wet-etching method through the first opening portion 60to form a second opening portion 62, the lower portion of the firstsidewall-insulation film 61 a becomes protruded from the second openingportion 62. If a dissimilar crystalline layer such as SiGe is made togrow in such a state that a protrusion amount of this firstsidewall-insulation film 61 a exceeds one half the thickness of thesilicon nitride film 55, as shown in FIG. 26, the firstsidewall-insulation film 61 a becomes an obstacle and the epitaxialgrowth on an outer circumferential portion of the second opening portion62 is blocked. Consequently, it is feared that a single crystalline SiGelayer 63 a and a polycrystalline SiGe layer 63 b are not connected.Therefore, base resistance at a link-base portion is markedly increased.FIG. 27 shows gammel plots of a HBT having been link-base contactfailure due to the protrusion of the first sidewall-insulation film 61 aand a normal HBT. Each of abnormal Ic and Ib characteristics in a regionwhere a voltage V_(BE) across base-emitter terminals is 0.7 V or moreindicates an extreme increase of base resistance.

Next, a description will be made of the reasons why the etchingselective ratio of the polycrystalline silicon film to the insulationfilm (silicon oxide film and silicon nitride film) lowers when thephotoresist film used as an etching mask is interposed therebetween inetching the polycrystalline silicon film by a chlorine (Cl)-based gas.FIGS. 28 through 31 indicate some models thereof. Reference symbol “70”of FIG. 28 shows a silicon oxide film, reference symbol “71” shows asilicon nitride film, and reference symbol “72” shows a surface of thesilicon oxide film 70.

The selective ratio when the polycrystalline silicon film is etched by adry-etching method using a chlorine-based gas can be explained by themagnitude of binding energy. When no photoresist film exists, Si—Clbinding energy (about 402 kJ/mol) is smaller than Si—O binding energy(465 kJ/mol). Consequently, an etching rate of SiO₂ by Cl is extremelyslow. That is, the selective ratio is great. In contrast, when thephotoresist film is used as an etching mask, carbon(C) exists in areaction system. That is, since a surface of a photoresist pattern 59 isstruck in a dry-etching treatment, as shown in FIGS. 28 and 29, carbonis discharged from the photoresist pattern 59 into a chamber. Meanwhile,since the C—O binding energy (1077 kJ/mol) is stronger than the Si—Obinding energy, a Si—O binding force weakens as shown in FIG. 30 if abond of C—O is formed on the surface 72 of the silicon oxide film 70. Ifthe Si—O binding force weakens, a bond of Si—Cl is formed and etching ofthe silicon oxide film 70 advances as shown in FIG. 31. That is, theetching selective ratio of the polycrystalline silicon film 56 to thesilicon oxide film 70 lowers. This phenomenon becomes more prominent ifthe silicon nitride film is replaced with the silicon oxide film 70.Consequently, as shown in FIG. 23, when the silicon oxide film 58 andthe lower polycrystalline silicon film 56 are etched by using thephotoresist pattern 59 as an etching mask in forming the first openingportion 60, an upper portion of the underlying silicon nitride film 55also is excessively etched, which results in occurrence of theabove-mentioned problems.

Therefore, in the present embodiment, the sidewall-insulation filmformed on the side surface of the first opening portion is preventedfrom blocking the growth of the dissimilar crystalline layer formed inthe second opening portion. As one example for this, the photoresistfilm is not used as an etching mask and the hard mask is used as anetching mask to form the first opening portion. In addition, the lengthof the portion of the sidewall-insulation film protruded to a side ofthe second opening portion is adjusted so that blocking of the growth ofdissimilar crystalline layer is prevented. Hereinafter, one specificexample of a manufacturing method for the semiconductor device accordingto the present embodiment will be described.

The semiconductor device of the present embodiment is one used fortelecommunication equipment such as optical transmission systems(photoelectric transfer apparatus etc.), cellular phones, high-frequencydiscrete products (VCO: voltage controlled oscillator or high-frequencyamplifier circuits, etc.), radio (RF: radio frequency) telecommunicationequipment (wireless LAN (local area network) or electronic equipment forBluetooth, etc.).

In this case, a manufacturing method for a semiconductor device havingan npn-type HBT (hetero-junction bipolar transistor), which can achievea high-speed operation, is illustrated. However, the present inventioncan be applied also to a manufacturing method for a semiconductor devicehaving a pnp-type HBT. FIGS. 1 through 15 are sectional views showing aprincipal portion in the manufacturing process of a semiconductordevice, and FIG. 16 is a plan view showing a principal portion of thesemiconductor device of FIG. 15. As shown in FIG. 1, the semiconductorsubstrate (hereinafter abbreviated as “substrate”) 1 is, for example, anearly plane circular SOI (silicon on insulator) wafer. That is, thesubstrate 1 has a semiconductor layer 1 c on a support substrate 1 a viaan insulation layer 1 b. The support substrate 1 a is made from, forexample, single crystalline silicon (Si) and has a function to securemechanical strength of the substrate 1. The insulation layer 1 b is madefrom, for example, a silicon oxide (SiO_(x)) film. The semiconductorlayer 1 c is made from, for example, a single crystalline silicon layerand has a semiconductor layer formed with the semiconductor wafer and anupper semiconductor layer thereof formed by an epitaxial method. On amain surface of this semiconductor layer 1 c (that is, the main surfaceof the substrate 1), a device is formed. In an isolation region of themain surface (device forming surface) of the semiconductor layer 1 c, ashallow isolation 2 a and a deep trench isolation 2 b are formed. Theshallow isolation 2 a is made from a silicon oxide film formed by, forexample, a LOCOS (local oxidization of silicon) method. By thisisolation 2 a, a plane range of an active region is defined. Inaddition, the deep trench isolation 2 b is formed by embedding, forexample, a silicon oxide film in a deep trench dug so as to reach theinsulation layer 1 b through the isolation 2 a and the semiconductorlayer 1 c from the upper surface of the isolation 2 a. By this deeptrench isolation 2 b, each device region in the semiconductor layer 1 cis completely separated electrically. Note that the isolation 2 a may beformed into a so-called shallow groove isolation (SGI) which is formedby embedding, for example, a silicon oxide film inside a shallow trenchdug in the semiconductor layer 1 c to such an extent as not to contactwith the insulation layer 1 b. In the semiconductor layer 1 c of an HBTregion, an n⁺-type collector embedding region 3 a is formed. In thiscollector embedding region 3 a, for example, antimony (Sb) is contained.On an upper layer of the collector embedding region 3 a, the n⁻-typecollector region (first semiconductor region) 3 b and the n⁺-typecollector extraction region 3 c are formed. In this collector region 3 band the collector extraction region 3 c, for example, phosphorous (P) iscontained. The collector region 3 b and the collector extraction region3 c are separated by the isolation 2 a provided therebetween andelectrically connected through the collector embedding region 3 a.

First, on the main surface of this kind of substrate 1 (SOI wafer), anabout 95 nm thick insulation film (first insulation film) 4 made from,for example, a silicon oxide film etc., an about 200 nm thick conductorfilm (first semiconductor film, first polycrystalline silicon film) 5made from, for example, a p⁺-type polycrystalline silicon film etc., anabout 100 nm thick insulation film (second insulation film, thirdinsulation film) 6 made from a silicon nitride film etc., and an about100 nm thick insulation film (fifth insulation film) 7 made from asilicon oxide film etc. are stacked up successively in this order fromthe bottom layer by a CVD (chemical vapor deposition) process etc.Subsequently, on the insulation film 7, a photoresist pattern(hereinafter abbreviated as “resist pattern”) FR1, from which the firstopening forming region is exposed and with which other region except itis covered, is formed by a photo-lithography technique (hereinafterabbreviated as “lithography technique”). Thereafter, as shown in FIG. 2,the resist pattern FR1 is used as an etching mask and the insulationfilms 7 and 6 exposed from it are etched successively by an anisotropicdry-etching treatment. Upon completion of the etching, the resistpattern FR1 is removed by ashing etc., as shown in FIG. 3.

Next, the uppermost insulation film 7 made from a silicon oxide filmetc. is used as an etching mask (hard mask) and the conductor film 5exposed therefrom is etched by an anisotropic dry-etching treatment toform the first opening portion 8 a, as shown in FIG. 4. As describedabove, in the present embodiment, by using the insulation film 7 madefrom a silicon oxide film etc. as an etching mask in this etchingtreatment, the etching selective ratio of the conductor film 5 made froma polycrystalline silicon film etc. to the lower insulation film 4 madefrom a silicon oxide film etc. can be greatly improved than that in thecase where the above-mentioned resist pattern is used as an etchingmask. For example, even in the same high-density plasma etchingapparatus, a selective ratio of the conductor film 5 to the insulationfilm 4 is 7 when the resist pattern is used as an etching mask, whereasthe selective ratio is about three times greater when the insulationfilm 7 made from a silicon oxide film etc. is used as an etching mask,that is, can is increased up to 20. Consequently, a scraping amount ofthe upper portion of the insulation film 4 on the bottom surface of thefirst opening portion 8 a can be eminently reduced. In addition,stability of the scraping amount of the upper portion of the insulationfilm 4 can be improved, whereby a processing with good reproducibilitycan be achieved. FIG. 5 is an enlarged sectional view of the principalportion of FIG. 4. In the present embodiment, the scraping amount d1 ofthe upper surface of the insulation film 4 on the bottom portion of thefirst opening portion 8 a is set to be within a range of 0<d1≦d2/2 where“d2” denotes the thickness the insulation film 4 in a directionorthogonal to the main surface of the semiconductor layer 1 c. That is,the scraping amount d1 is greater than 0 (zero) and is equal to orsmaller than one half the thickness d2 of the insulation film 4.According to the examination of the present inventors, for example, whenthe about 200 nm thick conductor film 5 made from a polycrystallinesilicon film etc. is etched, the scraping amount d1 of the insulationfilm 4 made from an about 100 nm thick silicon oxide film etc. has beencapable of constantly being reduced to 20 nm or less. That is, thescraping amount d1 of the insulation film 4 can be reduced to ⅕ or lessof the thickness d2 of the insulation film 4, whereby a sufficientmargin can be secured. Note that the first opening portion 8 a has aplane size of, for example, about 0.5 μm×about 2.0 μm.

Then, an about 50 nm thick insulation film made from, for example, asilicon nitride film etc. is deposited over the main surface of thesubstrate 1 (SOI wafer) by a CVD process etc., and then the insulationfilm is etch-backed by an anisotropic dry-etching method, and, as shownin FIG. 6, sidewall insulation films (second insulation film, fourthinsulation film, and sixth insulation film) 9 are formed on innersurfaces (first surface and third surface) of the first opening portion8 a. Subsequently, a wet-etching treatment is performed to the substrate1 by, for example, hydrofluoric acid (HF) to remove a portion of theinsulation film 4 through the first opening portion 8 a, and the secondopening portion (opening portion) 8 b greater in a plane size than thefirst opening portion 8 a is, as shown in FIG. 7, formed so as tocommunicate with the first opening portion 8 a. From the inside of thesecond opening portion 8 b, a portion of the main surface (activeregion) of the semiconductor layer 1 c is exposed. In addition, by thisetching treatment, an over-etching treatment is performed so that theetching of the insulation film 4 extends even to a portion of the lowerside of the conductor film 5, that is, undercut is formed. Consequently,an end portion of the conductor film 5 is protruded and extends likeeaves from an outer circumferential end of the second opening portion 8b toward the center of the second opening portion 8 b, and a surfaceopposite to the substrate 1 (second surface) is exposed from a protrudedportion thereof. In addition, in the present embodiment, a lower endportion of the sidewall-insulation film 9 is slightly protruded from thesecond surface of the conductor film 5 toward the main surface of thesemiconductor layer 1 c. That is, a portion of the sidewall-insulationfilm 9 is slightly protruded to a side of the second opening portion 8b. The protrusion amount on a lower end side of this sidewall-insulationfilm 9 corresponds to the above-mentioned scraping amount d1. That is,the protrusion amount on the lower end side of the sidewall-insulationfilm 9 is greater than 0 (zero) and is equal to or smaller than one halfthe thickness d2 of the insulation film 4. The thickness of thisinsulation film 4 corresponds to height h1 (height of the second openingportion 8 b) from the main surface of the semiconductor layer 1 c to thelower surface of the protruded portion of the conductor film 5 in thesecond opening portion 8 b. In addition, since the insulation film 7 ismade from the same silicon oxide film as the insulation film 4, it isall removed by the wet-etching treatment. However, in the presentembodiment, at this stage, the insulation film 6 made from a siliconnitride film etc. is deposited on the upper surface of the conductorfilm 5 and further the sidewall-insulation film 9 made from a siliconnitride film etc. is formed on the side surfaces (first surface andthird surface) of the conductor film 5 and the insulation film 6 in thefirst opening portion 8 a in such a manner to cover the entirety ofthem. In this case, the sidewall-insulation film 9 is formed so as tooverlap with a side surface (third surface) of the insulation film 6 inthe first opening portion 8 a with its upper portion being protrudedfrom the upper surface of the insulation film 6. Thus, since the uppersurface of the conductor film 15 and the inner surfaces (first surfaceand third surface) of the first opening portion 8 a are tightly coveredwith the insulation film 6 and the sidewall-insulation film 9 made froma silicon nitride film, the above-mentioned wet-etching treatment can besatisfactorily performed. Consequently, since a hydrogen-terminated andchemically stable surface of silicon of the semiconductor layer 1 c canbe more successfully exposed, effects due the hydrogen-terminatedsurface can be still more effectively exerted during the subsequentgrowth of the dissimilar crystalline layer, whereby satisfactory crystalgrowth can be promoted.

Next, after housing the substrate 1 (SOI wafer) in a chamber of anepitaxial growing apparatus for a dissimilar crystal growth treatment,annealing is performed for a short time by a lamp-annealing method etc.in an atmosphere containing a reducing gas such as a hydrogen gas. Thisheating treatment is also called a “reducing cleaning treatment”, and aprimary purpose thereof intends to remove the silicon oxide film on thedissimilar crystal growing surface (main surface of the semiconductorlayer 1 c) by a reduction reaction etc. and expose a clean siliconsurface on the crystal growing surface. Subsequently, as shown in FIG.8, in the treatment chamber of the epitaxial growing apparatus, thedissimilar crystalline layer (semiconductor film) 10 such assilicon-germanium (SiGe) is mad to selectively epitaxial-grow on thesemiconductor layer 1 c of the substrate 1 (SOI wafer) by, for example,a LP-CVD (low pressure-chemical vapor deposition) method. At the time ofthis selective SiGe growth, for example, SiH₂Cl₂, SiH₄, HCl, GeH₄, B₂H₆,H₂, or the like is used as a material gas. In this growth treatment, asingle crystalline layer (third semiconductor film) 10 a grows on themain surface of the semiconductor layer 1 c, and a polycrystalline layer(second semiconductor layer) 10 b grows on an exposed surface (secondsurface) of the portion of the upper surface side of the conductor film5, and these films are joined to form the dissimilar crystalline layer10. The single crystalline layer 10 a has, for example, an i(intrinsic)-SiGe layer, a p-type SiGe layer, and an i (intrinsic)-Silayer which are made to grow in this order from the lower layer. Thep-type SiGe layer of this single crystalline layer 10 a is a portionwhich becomes an HBT base region (true base region). In this p-type SiGelayer, for example, boron is introduced, and the concentration thereofis, for example, about 2×10¹⁹ cm⁻³. In addition, the uppermost i-Silayer is a portion at which the HBT emitter region is basically formed.Meanwhile, the polycrystalline layer 10 b is a portion that becomes alink-base portion formed by the growth of polycrystalline SiGe. Thegrowth is finished at the time when these single crystalline layer 10 aand polycrystalline layer 10 b are connected to each other. At thistime, in the present embodiment, growth of the dissimilar crystallinelayer 10, in particular, growth of the polycrystalline layer 10 b is notblocked, by setting so that the protrusion amount on the lower end sideof the sidewall-insulation film 9 is equal to or smaller than one halfthe thickness d2 of the insulation film 4. Consequently, thepolycrystalline layer 10 b can be made to successfully grow.Accordingly, since the polycrystalline layer 10 b and the singlecrystalline layer 10 a can be securely connected, the contact resistanceat the HBT link-base portion (portion of the polycrystalline layer 10 b)can be considerably reduced. In addition, if the upper surface of theconductor film 5 or a side surface of the first opening portion 8 a isexposed even partially, the dissimilar crystalline layer is made to growfrom the exposed surface at the time of the growth of the dissimilarcrystalline layer. In particular in the conductor film 5, since uppercorners on a side of the first opening portion 8 a are easily exposed,the unnecessary dissimilar crystalline layer is made to grow therefromin some cases. The growth of this unnecessary dissimilar crystallinelayer causes short-circuit failure between a base and an emitter. Asagainst this, in the present embodiment, the sidewall-insulation film 9is formed so as to overlap with side surfaces of the insulation film 6and the conductor film 5 in the first opening portion 8 a, and thesidewall-insulation film 9 is provided so as to securely cover the uppersurface of the conductor film 5 and the inner surface of the firstopening portion 8 a. Therefore, it is possible to prevent the dissimilarcrystalline layer 10 from growing at some unnecessary places. That is,selective growth of the dissimilar crystalline layer 10 can besatisfactorily performed. Note that the resistance of the conductor film5 is reduced by being further diffused to such an extent that theimpurity (boron) in the conductor film 5 for forming the base electrodereaches the insulation film 4 during the selective growth of thedissimilar crystalline layer 10.

However, main elements of the dissimilar crystalline layer 10 are notlimited to SiGe and can be variously altered and, for example, Si orsilicon-germanium-carbon (SiGeC) may be used. If Si is used, i(intrinsic)-Si, P-type Si, and i (intrinsic)-Si are made to growsubsequently in this order from the lower layer to form the singlecrystalline layer 10 a of the dissimilar crystalline layer 10. Inaddition, if SiGeC is used, i (intrinsic)-SiGeC, P-type SiGeC, and i(intrinsic)-Si are made to grow subsequently in this order from thelower layer to form the single crystalline layer 10 a of the dissimilarcrystalline layer 10. If the main element of the dissimilar crystallinelayer 10 is a SiGe layer, cutoff frequency characteristics (fT) andcurrent gain (hFE) can be improved as compared to the case in which Siis used. In addition, when Si is used, the temperature characteristicscan be improved. Furthermore, if SiGeC is used, a concentration of Gecan be increased as compared to the case in which SiGe is used.Therefore, the cutoff frequency characteristics (fT) and the currentgain (hFE) can be further improved.

Next, as shown in FIG. 9, after depositing an insulation film (seventhinsulation film) 11 made from, for example, a silicon oxide film etc. onthe main surface of the substrate 1 (SOI wafer) by a CVD process etc.,the true collector region right below the base is selectively increasedup to a high concentration by using this insulation film 11 as a throughfilm and by ion-injecting, for example, phosphorus (P) into thesemiconductor layer 1 c. This ion-injection treatment is a treatment forforming an SIC (selective implanted collector) region 12 in thesemiconductor layer 1 c. Thereby, the HBT frequency characteristics canbe improved. In addition, the collector resistance can be reduced, too.Subsequently, for example, a low-resistance polycrystalline silicon filmis deposited on the main surface of the substrate 1 by a CVD processetc., and thereafter is etched back by an anisotropic dry-etching methodto form a sidewall-conductor film (fifth semiconductor film) 13 madefrom a low-resistance polycrystalline silicon film etc. on the sidesurface of the first opening portion 8 a via the sidewall-insulationfilm 9 and the insulation film 11, as shown in FIG. 10. At this time,since the surface of the dissimilar crystalline layer 10 is protected bythe insulation film 11, damage by dry-etching can be prevented.Thereafter, the wet-etching treatment is performed to the substrate 1and the insulation film 11 exposed from the sidewall-conductor film 13is selectively etched as shown in FIG. 11, whereby an emitter openingportion (third opening portion) 14 is formed. From the emitter openingportion 14, the single crystalline layer 10 a of the dissimilarcrystalline layer 10 is exposed. Since the emitter opening portion 14 isformed by a wet-etching treatment, the exposed surface of the dissimilarcrystalline layer 10 is not subject to damage.

Then, on the main surface of the substrate 1 (SOI wafer), a conductorfilm made from a phosphorus-doped polycrystalline silicon film having athickness of, for example, about 250 nm is deposited on a side of themain surface of the substrate 1 by a CVD method. Then, as shown in FIG.12, the conductor film is processed by a dry-etching method using aresist pattern FR2 as an etching mask to form emitter extractionelectrodes (fourth semiconductor film, sixth semiconductor film, secondelectrode, and emitter electrode) 15E. The bottom surface of the emitterextraction electrode 15 contacts with the above-mentioned i-Si layer ofthe dissimilar crystalline layer 10 through the emitter opening portion14. Subsequently, the resist pattern FR2 is removed by ashing andthereafter, as shown in FIG. 13, the insulation film 6 and the conductorfilm 5 are etched by a dry-etching method using a resist pattern FR3 asan etching mask to form base extraction electrodes (first semiconductorlayer, first electrode, first polycrystalline silicon film, and baseelectrode) 5B. In the present embodiment, the upper surface of the baseextraction electrode 5B and the side surface of the first openingportion 8 a are securely covered with the insulation film 6 and thesidewall-insulation film 9, respectively. Therefore, it is possible tosufficiently secure withstand resistance between the base extractionelectrode 5B and the emitter extraction electrode 15E and to preventshort-circuit failure between these electrodes. Subsequently, afterremoving the resist pattern FR3, a heat treatment is performed to thesubstrate 1 (SOI wafer) at, for example, 900° C. for about 30 seconds.Thereby, phosphorus in the emitter extraction electrode 15E is diffusedin the i-Si layer of the dissimilar crystalline layer 10 and, as shownin FIG. 14, a single crystalline emitter region 16 is formed at an upperportion (a region contacting with the emitter extraction electrode 15E)of the dissimilar crystalline layer 10. The HBT17 is thus formed on thesubstrate 1 (SOI wafer). Thereafter, as shown in FIGS. 15 and 16, afterdepositing the insulation film 18 made from, for example, a siliconoxide film etc. on the main surface of the substrate 1 by a CVD methodetc., contact holes CNT are formed on the insulation film 18 to exposethe base extraction electrode 5B, the emitter extraction electrode 15E,and the collector extraction region 3 c.

Next, for example, tungsten (W) is deposited on the main surface of thesubstrate 1 (SOI wafer) by a CVD process etc. and then is scraped by aCMP or etch-back method, so that plugs 19, each made from tungsten etc.,are formed in the contact holes CNT. Subsequently, on the main surfaceof the substrate 1 (SOI wafer), a barrier conductor film such astitanium tungsten (TiW), an aluminum-based, relatively thick mainconductor film such as aluminum-silicon-copper alloy, and a barrierconductor film such as titanium tungsten are deposited subsequently inthis order from the lower layer by a sputtering method etc. Thereafter,since a laminated conductor film thereof is patterned by a lithographytechnique and a dry-etching method, first layer wirings M1 are formed.Note that since FIG. 16 shows a design drawing, each planar shape of theemitter opening portion 14, the first opening portion 8 a, and thecontact holes CNT, etc. is shown in a rectangular shape. However, suchshapes actually become ones without corners.

Thus, according to the present embodiment, the base resistance (inparticular, connection resistance between the link-base portion and thebase extraction electrode 5B) can be greatly reduced. Also, insulativeresistance properties between the base extraction electrode 5B and theemitter extraction electrode 15E can be satisfactorily secured and theshort-circuit failure between these electrodes can be prevented.Therefore, performance, reliability, and yield of the semiconductordevice having the HBT 17 can be greatly improved.

As described above, the invention made by the inventors has beenspecifically described based on the embodiment. However, needless tosay, the present invention is not limited to the above embodiment andcan be variously altered and modified without departing from the gistthereof.

For example, the description has been made of the case where thesubstrate comprises the SOI wafer. However, the substrate is not limitedto this case and can be variously changed and may be, for example, aregular substrate constituted by a semiconductor or an epitaxialsubstrate having an epitaxial layer provided on a surface of asemiconductor substrate.

In the above-mentioned description, there has been described the casewhere the invention made by the present inventors is mainly applied tothe manufacturing method for the semiconductor device having the HBT,which is the background and the applicable field of the invention.However, the invention is not limited to this case and can be applied toa manufacturing method for a semiconductor device that provides, forexample, a HBT and other elements to the same substrate. In addition,the invention is not limited to application to the telecommunicationequipment and, for example, can be applied to other informationprocessing equipment such as computers or digital cameras.

INDUSTRIAL APPLICABILITY

The present invention is useful as a manufacturing method of asemiconductor device which constitutes telecommunication equipment suchas optical transmission systems and cellular phones or as amanufacturing method of a semiconductor device which constitutesinformation processing equipment such as computers and digital cameras,and, in particular, is suitable for the use as a manufacturing method ofa semiconductor device having a HBT.

1. A semiconductor device comprising: (a) a first semiconductor regionhaving a first conductivity type formed over a semiconductor substrate;(b) a first insulation film deposited over said semiconductor substrate;(c) an opening portion opened in said first insulation film; (d) a firstsemiconductor film having a second conductivity type that is aconductivity type opposite to said first conductivity type, providedover said first insulation film, and extending so that a portion thereofis protruded from an end of said opening portion toward a center of theopening portion; (e) a second semiconductor film having the secondconductivity type formed toward a main surface of said semiconductorsubstrate with a surface of a protruded portion of said firstsemiconductor film contacting with a surface opposite to saidsemiconductor substrate; (f) a third semiconductor film having thesecond conductivity type formed so as to contact with the main surfaceof said semiconductor substrate and said second semiconductor film; and(g) a second insulation film formed over said first semiconductor filmand a side surface of said first semiconductor film located over saidopening portion, (h) wherein, of said second insulation film formed overthe side surface of said first semiconductor film, length of a portionextending so as to protrude from a bottom surface of said firstsemiconductor film toward the main surface of said semiconductorsubstrate is equal to or smaller than one half of thickness of saidfirst insulation film in a direction intersecting with saidsemiconductor substrate.
 2. The semiconductor device according to claim1 wherein a fourth semiconductor film has the first conductivity type soas to be electrically connected to said third semiconductor film andinsulated from said first semiconductor film.
 3. The semiconductordevice according to claim 1, wherein the second insulation film formedover the side surface of said first semiconductor film is protrudedupward from an upper surface of the second insulation film over saidfirst semiconductor film.
 4. The semiconductor device according to claim1, wherein said second semiconductor film is made from a silicon nitridefilm.
 5. The semiconductor device according to claim 1, wherein saidsecond semiconductor film is made from a poly crystal.
 6. Thesemiconductor device according to claim 1, wherein said thirdsemiconductor film is made from a single crystal.
 7. The semiconductordevice according to claim 1, wherein said second and third semiconductorfilms are each made from a material primarily containingsilicon-germanium.
 8. A semiconductor device comprising: (a) a firstsemiconductor region of a first conductivity type formed over asemiconductor substrate; (b) a first insulation film deposited over saidsemiconductor substrate; (c) an opening portion opened in said firstinsulation film; (d) a first electrode of a second conductivity typethat is a conductivity type opposite to said first conductivity type,located over said first insulation film, and extending so that a portionthereof is protruded from an end of said opening portion toward a centerof the opening portion; (e) a third semiconductor film located over saidfirst electrode; (f) a semiconductor film provided in said openingportion, electrically connected through a protruded portion of saidfirst electrode, and electrically connected to said first semiconductorregion; and (g) a fourth insulation film provided over a first surfaceintersecting with a main surface of said semiconductor substrate in asurface of a protruded portion of said first electrode, extending so asto protrude toward the main surface of said semiconductor substrate froma second surface opposite to said semiconductor substrate in the surfaceof said protruded portion of said first electrode, and provided so thatlength of the protruded portion is equal to or smaller than one half ofthickness of said first insulation film.
 9. The semiconductor deviceaccording to claim 8, wherein a second electrode of the firstconductivity type is provided so as to be electrically connected to saidsemiconductor film and insulated from said first electrode.
 10. Thesemiconductor device according to claim 8, Wherein said fourthinsulation film is a surface of a protruded portion of said thirdinsulation film located over the protruded portion of said firstelectrode, the surface being provided so as to overlap with a thirdsurface intersecting with the main surface of said semiconductorsubstrate.
 11. The semiconductor device according to claim 10, wherein aportion of said fourth insulation film protrudes from an upper surfaceof said third insulation film.
 12. The semiconductor device according toclaim 8, wherein said third and fourth insulation films are insulationfilms of the same kind and are insulation films of a kind different fromsaid first insulation film.
 13. The semiconductor device according toclaim 8, wherein said third and fourth insulation films are made fromsilicon nitride films.
 14. The semiconductor device according to claim8, wherein said semiconductor film is made from a material containingprimarily a semiconductor of a kind different from said semiconductorsubstrate.
 15. The semiconductor device according to claim 14, whereinsaid semiconductor film is made from a material containing primarilysilicon-germanium.
 16. The semiconductor device according to claim 8,wherein said semiconductor film has a second semiconductor film growingfrom said second surface of said first electrode, and a thirdsemiconductor film growing from the main surface of said semiconductorsubstrate so as to be connected to the second semiconductor film. 17.The semiconductor device according to claim 16, wherein said secondsemiconductor film is made from a poly crystal and said thirdsemiconductor film is made from a single crystal.
 18. A semiconductordevice having a bipolar transistor, comprising: (a) a firstsemiconductor region which is a collector region of said bipolartransistor and is of a first conductivity type formed over saidsemiconductor substrate; (b) a silicon oxide film deposited over saidsemiconductor substrate; (c) an opening portion opened in said siliconoxide film; (d) a first polycrystalline silicon film provided over saidsilicon oxide film, having a second conductivity type which is aconductivity type opposite to said first conductivity type, andextending so that a portion thereof is protruded from an end portion ofsaid opening portion toward a center of said opening portion; (e) apolycrystalline silicon-germanium film of the second conductivity type,which is formed toward a main surface of said semiconductor substratewith a surface of a protruded portion of said first polycrystallinesilicon film contacting with a surface opposite to said semiconductorsubstrate; (f) a single crystalline silicon-germanium film of the secondconductivity type, which is formed so as to contact with the mainsurface of said semiconductor and said polycrystalline silicon-germaniumfilm; (g) silicon nitride films formed over said first polycrystallinesilicon film and a side surface of said first polycrystalline siliconfilm located over said opening portion, Wherein, of the silicon nitridefilm formed over the side surface of said first polycrystalline siliconfilm, length of a portion extending so as to protrude from a bottomsurface of said first polycrystalline silicon film toward the mainsurface of said semiconductor substrate is equal to or smaller than onehalf of thickness of said silicon oxide film in a direction intersectingwith said semiconductor substrate, and said silicon nitride film formedover the side surface of said first polycrystalline silicon filmprotrudes upward from an upper surface of said silicon nitride film oversaid first polycrystalline silicon film.
 19. A semiconductor devicehaving a bipolar transistor, comprising: (a) a collector region of afirst conductivity type formed over said semiconductor substrate; (b) afirst insulation film deposited over said semiconductor substrate; (c)an opening portion opened in said first insulation film; (d) a baseelectrode having a second conductivity type that is a conductivity typeopposite to said first conductivity type, provided over said firstinsulation film, and formed so that a portion thereof extends andprotrudes from an end portion of said opening portion toward a center ofsaid opening portion; (e) a third semiconductor film provided over saidbase electrode; (f) a semiconductor film formed with said base electrodeand said corrector region in said opening portion contacting with eachother; (g) a base region of the second conductivity type, which isformed over said semiconductor film and electrically connected through aprotruded portion of said base electrode; (h) an emitter region of thefirst conductivity type, which is formed in said base region of saidsemiconductor film; and (i) an emitter electrode of the firstconductivity type, which is electrically connected to said emitterregion and insulated from said base electrode; and (j) a fourthinsulation film provided over a first surface which is a surface of theprotruded portion of said base electrode and intersects with a mainsurface of said semiconductor substrate, wherein the fourth insulationfilm is provided so that length of a portion, which extends so as toprotrude toward a main surface of said semiconductor substrate from asecond surface that is a surface of the protruded portion of said baseelectrode and is opposite to said semiconductor substrate, is equal toor smaller than one half of thickness of said first insulation film. 20.The semiconductor device according to claim 19, wherein said fourthinsulation film is provided so as to overlap with a third surface thatis a surface of said third insulation film over a protruded portion ofsaid base electrode and intersects with the main surface of saidsemiconductor substrate.
 21. The semiconductor device according to claim19, wherein a portion of said fourth insulation film protrudes from anupper surface of said third insulation film.
 22. The semiconductordevice according to claim 19, wherein said third and fourth insulationfilms are insulation films of the same kind and are insulation films ofa kind different from said first insulation film.
 23. The semiconductordevice according to claim 19, wherein said third and fourth insulationfilms are made from silicon nitride films.
 24. The semiconductor deviceaccording to claim 19, wherein said semiconductor film is made from amaterial containing primarily a semiconductor of a kind different fromsaid semiconductor substrate.
 25. The semiconductor device according toclaim 19, wherein said semiconductor film is made from a materialcontaining primarily silicon-germanium.
 26. The semiconductor deviceaccording to claim 19, wherein said semiconductor film has a secondsemiconductor film growing from said second surface of said baseelectrode and a third semiconductor film growing from the main surfaceof said semiconductor substrate so as to be connected to the secondsemiconductor film.
 27. The semiconductor device according to claim 26,wherein said second semiconductor film is made from a poly crystal andsaid third semiconductor film is made from a single crystal.
 28. Amanufacturing method for a semiconductor device, comprising the stepsof: (a) forming a first semiconductor region of a first conductivitytype over a semiconductor substrate; (b) depositing a first insulationfilm over a main surface of said semiconductor substrate; (c) depositinga first semiconductor film of a second conductivity type opposite tosaid first conductivity type over said first insulation film; (d)depositing a third insulation film of a kind different from said firstinsulation film over said first semiconductor film; (e) depositing afifth insulation film capable of taking an etching selective ratio tosaid third insulation film over said third insulation film; (f) openingportions of said fifth insulation film and third insulation film by anetching method using a photoresist film as an etching mask; (g) removingsaid photoresist film, and thereafter removing said first semiconductorfilm exposed from the opening by using said fifth insulation film as anetching mask to form a first opening portion in said third and fifthinsulation films and said first semiconductor film; (h) forming a sixthinsulation film of a kind different from said first insulation film overa side surface of said first opening portion; (i) forming, over saidfirst insulation film, a second opening portion in which a surfaceopposite to the main surface of said semiconductor substrate and saidfirst semiconductor region in said first semiconductor film are exposed,by selectively etching a portion of said first insulation film throughsaid first opening portion using said third insulation film and sixthinsulation film as etching masks; and (j) forming a semiconductor filmin said second opening portion, Wherein, during a processing for formingsaid first opening portion, an amount in which a portion of said firstinsulation film exposed from said first opening portion is etched and aprotrusion amount of said sixth insulation film protruding from asurface opposite to the main surface of said semiconductor substratetoward the main surface of said semiconductor substrate in said firstsemiconductor film are each set to be equal to or smaller than one halfof thickness of said first insulation film.
 29. The manufacturing methodfor a semiconductor device according to claim 28, further comprising thesteps of: (k) depositing a seventh insulation film over the main surfaceof said semiconductor substrate after said step (j); and (l) forming afifth semiconductor film of the first conductivity type via said sixthand seventh insulation films over the side surface of said first openingportion by a dry-etching method.
 30. The manufacturing method for asemiconductor device according to claim 29, further comprising: (m)removing, by the wet-etching method, said seventh insulation filmexposed from said fifth semiconductor film in said first opening portionafter the step (l), and forming a third opening portion from which aportion of said semiconductor film in said seventh insulation film isexposed; and (n) forming a sixth semiconductor film contacting with saidsemiconductor film and insulated from said first semiconductor filmafter said step (m).
 31. The manufacturing method for a semiconductordevice according to claim 30, wherein said first semiconductor region isa collector region of a bipolar transistor, said first semiconductorfilm is a base electrode of said bipolar transistor, and said sixthsemiconductor film is an emitter electrode of said bipolar transistor.32. The manufacturing method for a semiconductor device according toclaim 28, wherein said first and fifth insulation films are made fromsilicon oxide films and said third insulation film and sixth insulationfilm are made from silicon nitride films.
 33. The manufacturing methodfor a semiconductor device according to claim 28, wherein saidsemiconductor film is made from a material containing primarily asemiconductor of a kind different from said semiconductor substrate. 34.The manufacturing method for a semiconductor device according to claim33, wherein said semiconductor film is made from a material containingprimarily silicon-germanium.
 35. The manufacturing method for asemiconductor device according to claim 28, wherein said semiconductorfilm is formed by joining a second semiconductor film growing from asurface exposed from said second opening portion of said firstsemiconductor film and a third semiconductor film growing from the mainsurface of said semiconductor substrate.
 36. The manufacturing methodfor a semiconductor device according to claim 35, wherein said secondsemiconductor film is a poly crystal and said third semiconductor filmis a single crystal.
 37. The manufacturing method for a semiconductordevice according to claim 28, wherein said fifth insulation film is madefrom an insulative material of the same kind as said first insulationfilm.
 38. A manufacturing method for a semiconductor device, comprisingthe steps of: (a) forming a collector region of a first conductivitytype of a bipolar transistor over a semiconductor substrate; (b)depositing a first insulation film made from a silicon oxide film over amain surface of said semiconductor substrate; (c) depositing a firstsemiconductor film that is a conductive film for forming said bipolartransistor over said first insulation film, the first semiconductor filmbeing for forming a base electrode of a second conductivity typeopposite to said first conductivity type; (d) depositing a thirdinsulation film made from a silicon nitride film over said firstsemiconductor film; (e) depositing a fifth insulation film made from asilicon oxide film over said third insulation film; (f) opening portionsof said fifth insulation film and third insulation film by an etchingmethod using a photoresist film as an etching mask; (g) removing saidphotoresist film, thereafter removing said first semiconductor filmexposed from the opening by using said fifth insulation film as anetching mask, and forming a first opening portion in said third andfifth insulation films and said first semiconductor film; (h) forming asixth insulation film made from a silicon nitride film over a sidesurface of said first opening portion; (i) forming, in said firstinsulation film, a second opening portion, from which a surface oppositeto the main surface of said semiconductor substrate and said collectorregion in said first semiconductor film are exposed, by selectivelyetching a portion of said first insulation film through said firstopening portion using said third insulation film and sixth insulationfilm as etching masks; and (j) forming, in said second opening portion,a second polycrystalline semiconductor film growing from a surfaceexposed from said second opening portion of said first semiconductorfilm and forming a link base of said bipolar transistor and a thirdsingle crystalline semiconductor film growing from the main surface ofsaid semiconductor substrate and forming a true base region and emitterregion of said bipolar transistor, by an epitaxial growth method so thatthey are joined to each other, Wherein, during a processing for formingsaid first opening portion, an amount in which a portion of said firstinsulation film exposed from said first opening portion is exposed and aprotrusion amount of said sixth insulation film protruded from a surfaceopposite to the main surface of said semiconductor substrate toward themain surface of said semiconductor substrate in said first semiconductorfilm are equal to or smaller than one half of thickness of said firstinsulation film.
 39. The manufacturing method for a semiconductor deviceaccording to claim 38, further comprising the steps of: (k) depositing aseventh insulation film over the main surface of said semiconductorsubstrate after said step (j); and (l) forming a fifth semiconductorfilm of the first conductivity type via said sixth insulation film andseventh insulation film over the side surface of said first openingportion by a dry-etching method.
 40. The manufacturing method for asemiconductor device according to claim 39, further comprising the stepsof: (m) removing, in said first opening portion, said seventh insulationfilm exposed from said fifth semiconductor film by the wet-etchingmethod after said step (l), and forming a third opening portion, fromwhich a portion of said three semiconductor film is exposed, over saidseventh insulation film; and (n) forming a sixth semiconductor film forforming the emitter electrode, which contacts with said thirdsemiconductor film and is insulated from said first semiconductor filmafter said step (m).
 41. The semiconductor device according to claim 2,wherein a third insulation film is formed between said second insulationfilm and said fourth semiconductor film formed over a side surface ofsaid first semiconductor film.
 42. The semiconductor device according toclaim 9, wherein a fifth insulation film is formed between said fourthinsulation film and said second electrode.
 43. The semiconductor deviceaccording to claim 18, wherein an electrode to be an emitter regionformed over said single crystalline silicon-germanium film is formed,and an insulation film is further formed between the silicon nitridefilm and said electrode formed over a side surface of said firstpolycrystalline silicon film.
 44. The semiconductor device according toclaim 19, wherein a fifth insulation film is further formed between saidfourth insulation film and said emitter electrode.